Cadence Design Systems, Inc. develops electronic design automation (EDA) software and hardware. The company licenses software, as well as sells or leases hardware technology and provides design and methodology services throughout the world to help manage and accelerate electronics product development processes.
The company’s products and services are used by various electronics companies to design and develop complex integrated circuits, and personal and commercial electronics systems.
Products
The company offers customers three license types for its software: perpetual, term and subscription.
Incisive Functional Verification Platform
The Incisive functional verification platform enables its customers to employ enterprise-level verification process automation, including verification planning, management and process tracking with coordination of all verification activities across teams of specialists and different execution platforms.
The Incisive platform is targeted for three segments: design engineers using traditional hardware description languages and testing techniques; design teams that are also responsible for verification and need more automation; and multi-specialist enterprise teams comprised of systems, software, hardware verification, system validation, and logic design teams.
The Incisive platform includes verification process automation technologies, methodologies, and verification intellectual property, or IP, for many standard protocols.
The Incisive Design Team and Enterprise Manager: It automates and guides the verification process and then analyzes data, from planning to closure.
The Incisive Design Team and Enterprise Simulator: It offers mixed-language support, dynamic assertion checking, transaction-level support, HDL analysis and a complete debug environment.
The Incisive Formal Verifier: It shortens design and verification time while improving design quality by providing a formal means of verifying RTL functional correctness with assertions, without the need of testbench simulation, and also provides predictable, fast RTL block bring-up and assertion-based verification.
The Palladium and Extreme series of emulation and acceleration solutions: These accelerate the verification process and enable first working silicon with first working software.
Encounter Digital IC Design Platform
The Encounter digital IC design platform enables its customers to implement their digital nanometer-scale designs. It is based on a single user interface and unified in-memory data model, and is specifically designed to facilitate the analysis and optimization of chip performance, power consumption, and silicon area and manufacturability throughout its customers’ design processes.
The Encounter platform comprises various technologies, including Silicon virtual prototyping for enabling designers to plan the complete implementation of a chip before committing to a specific design strategy; Global register transfer level and physical synthesis for creating and physically locating logic on the chip, while simultaneously optimizing for performance, power, cost and yield; Signal integrity and yield-aware routing for connecting high performance physical interconnect between the logic gates; Signal integrity and nanometer delay analysis; Design-for-Test capability as well as post-silicon test diagnostics; and Logic Equivalence Checking and design constraint management capability for designers to verify that their RTL specification is equivalent to the final IC layout.
The Encounter platform supports hierarchical designs, with full-chip support for designs containing approximately 50 million gates (a gate is an electronic switch that allows or prevents the flow of electrical current in a circuit). The Encounter platform comprises three levels: Encounter L, XL and GXL. These levels are scaled to provide customers with technologies tailored to specific degrees of design complexity in the digital IC space.
Virtuoso Custom Design Platform
The Virtuoso custom design platform enables design predictability by ensuring that the circuit design representation would perform correctly in the final manufactured chip. With the Virtuoso platform, designers are able to deliver silicon-accurate analog, custom digital, radio frequency, or RF, and mixed-signal designs, while addressing the growing number of physical effects in package, power grid, interconnect, devices and substrate employing a top-down language-based design. The Virtuoso platform reduces design time by providing: Reference flows for analog, mixed-signal, RF and analog-digital integration focused at the wireless and analog/mixed-signal markets; Automatic analog circuit sizing and optimization (including yield optimization); Multi-mode simulation (digital, analog and RF) using a common syntax and model, and common equations; Fast custom layout technologies; Process migration technology; Electrical vs. physical effects analysis; and Physical design integration and silicon analysis for complex custom, cell-based and mixed custom designs.
Allegro System Interconnect Design Platform
The Allegro system interconnect design platform enables design teams to design high-performance interconnect across the domains of IC, package and PCB, reducing cost and time to market. The system interconnect — between input-output, buffers and across ICs, packages and PCBs — can be optimized through the platform’s co-design methodology, reducing both hardware costs and design cycles. Designers use the Allegro platform’s constraint-driven methodology and advanced capabilities for design capture, signal integrity and physical implementation. Silicon design-in kits to market by allowing IC companies to shorten new device adoption time and allowing systems companies to accelerate PCB system design cycles.
The system interconnect product group includes the Allegro system interconnect platform and the OrCAD product line of PCB design products which are engineered for individual or small design team productivity. The OrCAD product line is marketed worldwide through a network of alternative channel partners.
Design for Manufacturing (DFM)
The company’s products that deliver DFM capabilities for nanometer SoC design include: Fire & Ice QX and Assura RCX extraction products, which take the designer’s physical representation of an IC and extract the electrical properties of that design representation to enable further analyses, such as simulation and timing analysis; Products in the VoltageStorm family, which analyze on-chip power distribution for digital, analog and SoC designs. VoltageStorm detects unanticipated voltage drop, enabling the customer to correct fatal conditions, thereby preventing troubleshooting and delay during initial manufacturing; Physical verification products, including Cadence Physical Verification System, Assura, Diva and Dracula, which perform manufacturing design rule checks to ensure the proposed design meets the requirements of the foundry’s manufacturing process rules; Mask data preparation tools, such as MaskCompose and QuickView, which help customer mask shops create mask and reticle layouts for chips being manufactured in nanometer processes; and Design Virtual Interconnect Predictor, which helps customers understand the impact of chemical-metal planarization on their chip performance at advanced silicon geometries.
Kits
The company’s kits are designed to allow companies in these sectors to achieve shorter, predictable design cycles and design productivity by greatly simplifying the application and integration of EDA technologies and verification IP. Each kit addresses application-specific design issues by combining a verified methodology and enabling standards-based IP – all applied to a segment representative design and delivered with application consulting. The company’s kits include the AMS Methodology and RF Design Methodology Kits, as well as RF SiP Methodology Kit and the Functional Verification Kit for ARM.
Verification and Application Specific Programming Services
The company offers verification and applications specific programming, or ASP, services through Time-to-Market Engineering (TtME) services. Its TtME team provides customers with consulting services, project services and/or complete services for verification acceleration and system emulation. QuickCycles allows customers to access its Palladium simulation acceleration and emulation products on a pay-as-you-go basis, either on the customer internet site or remotely over a high-speed, secure network connection.
Third Party Programs and Initiatives
The company supports the integration of third party design products through its OpenAccess Initiative and Connections and OpenChoice programs. OpenAccess is a full-featured EDA database that supports access and manipulation of its internal EDA data via a fully documented and freely available programming interface. This provides an open application program interface through which applications developed by its customers, by their other EDA vendors, or by university research groups can operate within a single database and with Cadence platforms. It has licensed the OpenAccess database to the OpenAccess Coalition, which is operated by the Silicon Integration Initiative, an organization of EDA, electronic system and semiconductor industry focused on improving productivity and reducing cost in creating and producing integrated silicon systems.
The Connections Program provides other EDA companies with access to its products to ensure that its products work well with those third party tools.
Competition
The company competes in the EDA market for products and maintenance primarily with three other significant companies: Synopsys, Inc., Mentor Graphics Corporation and Magma Design Automation, Inc.
History
Cadence Design Systems, Inc. was founded in 1983.
